Sets the frequency of the clock synthesis output signal.
In addition to a numerical value, it is also possible to specify UP and DOWN. The frequency is then increased or decreased by the value which is set under CSYNthesis:FREQuency:STEP.
Parameters: | ||||||||
<Frequency> |
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Example: | CSYN:FREQ 500kHz sets the frequency of clock synthesis signal to 500kHz. | |||||||
Options: | R&S SMA-B29 | |||||||
Manual operation: | See "Frequency - Clock Synthesis" |
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