Activates/deactivates generation of a system clock for differential outputs CLK SYN and CLK SYN N at the rear of the instrument
Parameters: | ||||
<State> |
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Example: | CSYN:STAT ON a clock signal with the set frequency is output. | |||
Options: | R&S SMA-B29 | |||
Manual operation: | See "State - Clock Synthesis" |
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